The present invention relates to fault tolerant systems and particularly to a CMOS driver circuit for use as a spare or redundant circuit.
In high reliability applications, e.g., spacecraft, cold spare is the condition where a spare or redundant parts power supply, V.sub.DD, is connected to ground, V.sub.SS, and kept in unbiased storage until the part is needed. The power savings from not using power while in the cold spare mode as compared to providing a warm or hot standby circuit is an important benefit of the cold spare circuit.
The cold spare circuit output remains connected to an active signal or data bus while in the cold spare mode and must therefore present a high impedance to the active signal.
A problem occurs where a typical CMOS output driver having a p-channel transistor drive to a high data state, i.e., V.sub.DD or V.sub.CC and an n-channel transistor drive to a low data state, i.e., V.sub.SS.
FIG. 1 shows a typical CMOS output driver 1 including input 2, inverter 3, node A, inverter 4, node B, p-channel transistor P10, n-channel transistor N10, power supply connection V.sub.DD, ground connection V.sub.SS, and output 5.
FIG. 2 shows p-channel and n-channel MOS transistor schematic pin definitions as shown in the present patent application. The design of output driver 1 prevents using the part as a cold spare if the output node 5 to a package pin remains connected to an active signal or bus.
In FIG. 1, if V.sub.DD is connected to V.sub.SS but output node 5 remains connected to an active signal or bus as is the common situation, as an external output driver from another part on the signal or bus pin tries to drive the signal or bus, i.e., output node 5 high, the drain (D) to substrate (B) on junction of P10 will forward bias. Its substrate is connected to V.sub.DD, which is connected to V.sub.SS, resulting in a current path to V.sub.SS. P10 is typically a very wide transistor resulting in a low impedance path to V.sub.SS. The external driver will be unable to drive the signal or bus pin to a high state thereby preventing valid operation.
One proposed output driver in the past which does not use CMOS is shown in FIG. 6. The circuit of FIG. 6 only provides an output drive to V.sub.DD minus a bipolar junction transistor saturated VCE plus forward bias voltage drop. In addition, the circuit of FIG. 6 requires a diode type device and is implemented in BiCMOS technology.
Thus, a need exists for a CMOS driver circuit that provides a full CMOS output and can be used in a cold spare mode.